1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a trench gate fin field effect transistor (Trench-Gate Fin-FET).
2. Description of the Related Art
Recently, with a miniaturization of a transistor, it is being problematic that due to a so-called short channel effect, threshold voltage becomes lower and sub-threshold voltage characteristic becomes deteriorated. As a high-performance transistor suppressing such a problem, a fin field effect transistor (Fin-FET) has been remarked whose channel is fabricated in fin shape. Further, in order to use the Fin-FET as a transistor with a low leakage requirement such as a cell transistor of a dynamic random access memory (DRAM), Trench-Gate Fin-FET (also called as a saddle Fin-FET) is set forth which combines a trench gate structure with the fin structure (Japanese Patent Laid-Open No. 2008-47909, Japanese Patent Laid-Open No. 2008-16842, S-W Chung, et. al., Symposium on VLSI Tech. Dig., pp. 32-33, 2006, etc).
It is known that when a fin width becomes one-half or less of an effective channel length in the Fin-FET, performance of the Fin-FET becomes better (J. Kedzierski, et. al., IEEE Trans. Electron Device, vol. 50, pp 952-958, April 2003). However, in the Trench-Gate Fin-FET, a width of an active region itself becomes a fin width, and, hence, the fin width becomes larger relative to the effective channel length. That is, the advantage which occurred at the Fin-FET in making the transistor smaller may not be sufficiently taken.
Moreover, if the width of the entire active region becomes smaller in order to make the fin width smaller, contact resistance increases as a contact area is smaller, and, further, on-current decreases as an effective channel width becomes smaller. Especially in a semiconductor device with an embedded gate structure where resistance of a source and drain diffusion layer is high, such decreasing of the on-current becomes more outstanding when making the width of the active region smaller.
Accordingly, there exists a need to provide Trench-Gate Fin-FET where the advantage which shall be exerted in the Fin-FET can be sufficiently taken even if the transistor becomes finer and, at the same time, such decreasing of the on-current can be suppressed by saving a sufficiently large contact area in the active region.